1. Field of the Invention
The present invention relates to an insulated gate bipolar transistor (hereinafter referred to as IGBT), and more particularly, it relates to the structure of an IGBT which is suitably applied to a stroboscope and a method of manufacturing the same.
2. Description of the Background Art
In the field of a stroboscope, a system employing a self-arc-suppressing type element has been recently studied in place of a conventional thyristor system requiring a commutation circuit. Within such self-arc-suppressing type elements, particularly studied is a voltage-driven type IGBT, which can simplify a driving circuit and have high current capacity. However, a generally developed IGBT has been suitable for an inverter. An IGBT employed for an inverter is generally in non-latch type structure, in which main current enters a saturation region below latch-up current in order to effectuate self current limitation upon shorting. Thus, the generally developed IGBT is unsuitable for a stroboscope. Such a problem will be described hereinafter in detail.
FIG. 1 is a sectional view showing basic structure of a conventional N-channel IGBT. Referring to FIG. 1, a P.sup.+ -type semiconductor substrate 1 of relatively low specific resistance, which serves as a collector layer, is provided on one major surface thereof with an N.sup.+ -type buffer layer 2 of relatively low specific resistance for suppressing injection of positive holes from the collector layer 1, and an N-type body layer 3 of relatively high specific resistance is formed on the N.sup.+ -type buffer layer 2. A plurality of P-type base regions 4 are formed on the surface of the N-type body layer 3 by selectively introducing a P-type impurity in accordance with a prescribed pattern, and N.sup.+ -type emitter regions 5 of relatively low specific resistance are formed on the surfaces of the P-type base regions 4 by selectively introducing an N-type impurity. Surface parts 6 of the P-type base regions 4 held between the N.sup.+ -type emitter regions 5 and the N-type body layer 3 are defined as channel regions. A gate electrode 8 is provided on the channel regions 6 through a gate oxide film 7. Emitter electrodes 9 having emitter-short structure for preventing a latch-up phenomenon are formed on the N.sup.+ -type emitter regions 5 and the P-type base regions 4, and a collector electrode 10 is formed on the rear surface of the P.sup.+ -type collector layer 1.
In a general IGBT, a P-type region (P.sup.+ -type collector layer 1 in FIG. 1) is basically provided on a drain side of a vertical MOS-FET. In operation, the P.sup.+ -type collector layer 1 injects holes into the N-type body layer 3 through the N.sup.+ -type buffer layer 2 to cause modulation with electrons injected from the N.sup.+ -type emitter regions 5 through the channels 6 formed by application of voltage to the gate 8, to thereby extremely reduce resistance of the N-type body layer 3 (conductivity modulation effect). Resistance of the N-type body layer 3, which is a main cause for increase in ON resistance of a MOS-FET of high breakdown voltage, is thus extremely reduced, whereby the IGBT, which is a voltage control type element similarly to the MOS-FET, can implement high current capacity as compared with the MOS-PET, even if the same is formed as an element of high breakdown voltage.
In the IGBT, however, a parasitic thyristor is defined by the N.sup.+ -type emitter regions 5, the P-type base regions 4, the N-type body layer 3 and the P.sup.+ -type collector layer 1, as understood from FIG. 1. When main current (collector current) flowing in the IGBT is increased, hole current flowing from the N-type body layer 3 into the P-type base regions 4 is also increased. This hold current serves as gate current for the parasitic thyristor, which is turned on when the gate current exceeds a certain limit. Once the parasitic thyristor enters an ON state, it is impossible to control the main current by gate voltage which is applied to the gate 8 (e.i., latch-up phenomenon}, to lead to breakdown of the element.
FIG. 2 is a graph showing I.sub.C -V.sub.CE output characteristics of the IGBT. Symbol I.sub.C represents collector current and symbol V.sub.CE represents collector-to-emitter voltage. Both of the collector current I.sub.C and the collector-to-emitter voltage V.sub.CE are at normalized values. As obvious from FIG. 2, self current limitation is caused under constant gate voltage V.sub.G similarly to the case of the MOS-FET, whereby the collector current I.sub.C is not increased in excess of saturation current I.sub.C(sat). Thus, when latch-up current I.sub.L is higher than maximum saturation current I.sub.C(sat)4 in a prescribed gate voltage range V.sub.G1 to V.sub.G4 as shown by a dotted line in FIG. 2, no latch-up phenomenon can take place in such a gate voltage range. Thus, an IGBT of non-latch structure is implemented.
The latch-up phenomenon has been thus prevented in the conventional IGBT. The latch-up current I.sub.L, which depends on the structure of the IGBT, is generally about hundreds of amperes per cm.sup.2 in an IGBT developed for an inverter. In order to implement an IGBT of non-latch structure, therefore, the saturation current I.sub.C(sat) must be suppressed to be not more than hundreds of amperes per cm.sup.2 in a working gate voltage range. On the other hand, pulse energization ability of desirably at least 1000 A/cm.sup.2 is required for an IGBT for a stroboscope. Thus, if stroboscope is formed by using an IGBT whose saturation current I.sub.C(sat) is suppressed as hereinabove described, a problem is caused in insufficient pulse energization ability.